application the connor-winfield stratum 3+ simplified control timing module acts as a complete system clock module for stratum 3+ timing applications in accordance with gr-1244- core, issue 2 and gr-253-core, issue 3. connor-winfield?s stratum 3+ timing module helps reduce the cost of your design by minimizing your development time and maximizing your control of the system clock with our simplified design. features dual input references hitless switch over 8 khz - 38.88 mhz sync_out range 8 khz independent output 39 ppb composite hold over mode fast acquisition mode hold over good indicator lor alarms reference frequency limit alarm stratum 3+ timing module (stm-s3+, 3.3v) 2111 comprehensive drive aurora, illinois 60505 phone: 630- 851- 4722 fax: 630- 851- 5040 www.conwin.com bulletin tm040 page 1 of 10 revision p01 date 24 oct 02 issued by mbatts
preliminary data sheet #: tm040 p age 2 of 10 rev: p01 date: 10/24/02 ? copyright 2002 the connor-winfield corp. all rights reserved specifications subject to change without notice general description connor-winfield?s stm-s3+ timing module provides stratum 3+ synchronization for a complete system clock solution in a single module in accordance with gr-1244- core issue 2, and gr-253-core issue 3. the stm-s3+ provides a reliable network element clock reference to line cards used in tdm, pdh, sonet, and sdh application environments. typical applications include digital cross talks, dslams, adms, multiservice platforms, switches and routers. the stm-s3+ meets 39 ppb hold over requirements over 0 ? 70c temperature range. the 3.3v power requirement will draw a maximum of 1.6 a during an initial start-up period and then drop to a typical current of 1.2 a during normal operating conditions. it accepts two 8 khz input references and can be manufactured to supply a fixed frequency from 8 khz to 38.88 mhz. the stm-s3+ offers 4 user selectable modes of operation, reference 1, reference 2, hold over and free run. mode of operation is selected by two control pins (table 6). the current mode of operation is also indicated by two status pins (table 7). free run is the default mode if no control signals are asserted on the control pins. reference 1 mode and reference 2 mode are the two primary operating modes. when the module is locked to a valid reference, any time after initial power up or reset, the module is considered to be in the normal operating mode. during normal operation the output frequency is phase locked to the input reference frequency. the offset between the input and output is dependant upon the amount of noise that is present on the reference signal. for input tolerances, refer to table 4. hold over mode provides a stable frequency that is guaranteed to be within 0.039 ppm over the entire temperature range for the first 24 hours after entry into hold over. hold over is valid 101 seconds after a reference is selected and continues to do a running average every 8 seconds for the next 1049 seconds. long-term hold over values are based on a 1049 second moving window average. hold over values are not updated during lor or during fast acquisition mode. hold over values are buffered for at least 32 seconds to allow enough time to respond to the rfl alarm. free run is a mode of operation in which the module is not locked to a reference and its output frequency is solely dependent on the initial frequency setting of the internal oscillator. the output frequency in free run is guaranteed to be 4.6ppm of the nominal frequency. fast acquisition mode is entered whenever reference 1 or 2 has been selected. after a new reference has been selected, the module uses internal filtering that limits the frequency movement to less than 2.9 ppm/sec. by 100 seconds the module switches to a slower 0.1hz filter. while in normal mode, if the phase error is greater than 20 s, fast acquisition mode will be initiated. fast acquisition mode is further described as fast start mode in gr-1244-core, issue 3, sec 3.6. the stm-s3+ may be reset by asserting a logic low signal to the reset pin or cycling the power. using the reset pin for a manual reset is the recommend method for resetting the module. resetting the module by cycling the power requires more time due to the restablization of the internal ovenized oscillator. the stm-s3+ provides the user with non-interruptive tri- state capabilities. by asserting a logic high signal to the tri- state pin, the user is able to tri-state all outputs. while in tri-state, the module continues normal operations and accepts all normal inputs. when the module is released from tri-state, all output signals are valid. the stm-s3+ module provides three output frequencies. the sync_out is the primary synchronized output. it is phase locked to the input reference during normal operation and is set to a fixed frequency when operating in hold over or free run. clock_out provides a frequency output that comes from an independent, undisciplined, free running oscillator that is 4.6 ppm from the nominal frequency. this output is typically used for reference frequency qualification. the 8 khz output is derived from the sync_out output. the stm-s3+ module provides a variety of alarm indicators to alert the user to multiple conditions that may affect the overall performance of their system. the lor (loss of reference) alarm indicates that the active reference has been lost. rfl (reference frequency limit) indicates that the sync_out frequency is 15 ppm or more from the free run frequency. the mode alarm pin is used to indicate that the module is not in a normal operating mode. conditions that will cause the mode alarm to go high are hold over, free run, or fast acquisition modes. see table 8 for a full description of input control pins and output indicator pins. the hold over good pin indicates that an initial average has been acquired to provide a qualified hold over frequency. the module requires approximately 101 seconds from any reference switch or mode switch to a new reference to reacquire a valid average before the indicator goes high. initially, entry into hold over prior to this will result in a free run frequency. after the first hold over good indication, entry into hold over will be the last valid hold over frequency. the stm-s3+ meets the requirements for wander generation and wander transfer as required by gr-1244, sections 5.3 and 5.4. figures 4, 5 and 6 show typical results. it also complies with phase transient requirements during reference rearrangement, entry into hold over, and 1 s transient.
preliminary data sheet #: tm040 p age 3 of 10 rev: p01 date: 10/24/02 ? copyright 2002 the connor-winfield corp. all rights reserved specifications subject to change without notice notes: 1.0: stresses beyond those listed under absolute maximum rating may cause damage to the device. operation beyond recommended conditons is not implied. 2.0: logic is 3.3v cmos recommended operating conditions table 2 symbol parameter minimum nominal maximum units notes v cc power supply voltage 3.135 3.3 3.465 volts 6.0 v ih high level input voltage - cmos 2.0 5.5 volts v il low level input voltage - cmos 0 0.8 volts dc characteristics table 3 symbol parameter minimum nominal maximum units notes v oh high level output voltage, 2.4 3.3 3.6 volts 2.0 i oh = -4.0ma, v cc = min. v ol low level output voltage, 0.4 volts i ol = 8.0ma, v cc = max. specifications table 4 parameter specifications notes frequency range (sync_out) 8 khz - 38.88 mhz frequency range (clk_out) 8 khz - 51.84 mhz supply current 1.2 a typical, 1.6 a during warm-up (maximum) timing reference inputs gr-1244-core 3.2.1 jitter, wander and phase transient tolerances gr-1244-core 4.2-4.4, gr-253-core 5.4.4.3.6 wander generation gr-1244-core 5.3, gr-253-core 5.4.4.3.2 wander transfer gr-1244-core 5.4 jitter generation gr-1244-core 5.5, gr-253-core 5.6.2.3 jitter transfer gr-1244-core 5.5, gr-253-core 5.6.2.1 phase transients gr-1244-core 5.6, gr-253-core 5.4.4.3.3 sync_out (pin #15) free run accuracy 4.6 ppm over temperature range clock_out (pin #18) accuracy 4.6 ppm over temperature range hold over stability 0.012 ppm (5c), 0.039 ppm (0c - 70c) 3.0 inital offset 0.001 ppm 0.001 ppm temperature 0.010 ppm 0.035 ppm drift 0.001 ppm 0.003 ppm maximum hold over history 1049 seconds minimum time for hold over 101 seconds after a reference rearrangement pull-in/ hold-in range 17 ppm from free run frequency 4.0 lock time 100 sec. lock accuracy 0.01 ppm (gr-1244-core 2.8) 5.0 rfl alarm limit 15 ppm from free run frequency 3.0: hold over stability is the cumulative fractional frequency offset as described by gr-1244-core, 5.2 4.0: pull-in range is the maximum frequency deviation from nominal clock rate on the reference inputs to the timing module that can be overcome to pull into sychronization with the reference 5.0: after 100 seconds at stable temperature (5 f) 6.0: 5.0 v module also available absolute maximum rating table 1 symbol parameter minimum nominal maximum units notes v cc power supply voltage -0.3 4.0 volts 1.0, 6.0 v i input voltage -0.5 5.5 volts 1.0 t s storage temperature -40 85 deg. c 1.0
preliminary data sheet #: tm040 p age 4 of 10 rev: p01 date: 10/24/02 ? copyright 2002 the connor-winfield corp. all rights reserved specifications subject to change without notice pin description table 5 pin # connection description 1 status 0 mode indicator. 2 status 1 mode indicator. 3 lor loss of reference indicator. 1 = active reference has been lost. 4 future use reserved for future use. do not assert this pin. 5 gnd ground 6 8 khz output derived from sync_out. 7 reset master reset for the module. a low pulse will reset the module. a logic low for a minimum of 1 s is recommended to ensure a complete reset. this pin is pulled high internally. 8 tri-state tri-state control for all outputs. 1 = hi-z condition, 0 = normal operation. pin is pulled low internally. 9 hold over good indicates that the module has acquired enough data to provide an average hold over value. 10 mode alarm alarm indicator output. 1 = alarm condition, 0 = normal operation. 11 cntl a mode control input. pin is pulled low internally. 12 cntl b mode control input. pin is pulled low internally. 13 rfl reference frequency limit alarm for the phase locked loop. 1= unit is 15 ppm from free run freq. 14 gnd ground 15 sync_out system clock output 16 future use reserved for future use. do not assert this pin 17 gnd ground 18 clock_out an independent, stratum 3 clock output with the required 4.6 ppm accuracy. may be used as general purpose clock 19 future use reserved for future use. do not assert this pin 20 gnd ground 21 external reference 2 external reference #2 input 22 gnd ground 23 external reference 1 external reference #1 input 24 +3.3 v dc +3.3 volt dc supply status 1 status 0 mode 0 0 free run 0 1 reference 1 1 0 reference 2 1 1 hold over status outputs table 7 cntl b ctnl a mode selected 0 0 free run 0 1 reference 1 1 0 reference 2 1 1 hold over control inputs table 6
preliminary data sheet #: tm040 p age 5 of 10 rev: p01 date: 10/24/02 ? copyright 2002 the connor-winfield corp. all rights reserved specifications subject to change without notice status 0 status 1 lor future use 8 khz output reset tri-state hold over good mode alarm cntl a cntl b +3.3vdc external reference 1 gnd external reference 2 gnd future use clock_out gnd future use sync_out gnd rfl gnd 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 pin assignment figure 1 independent free run system clock network timing reference input eg. bits cntl a gnd rfl cntl b future use sync_out future use clock_out gnd hold over good mode alarm 8 khz output reset tri-state external reference 2 external reference 1 gnd gnd lor gnd future use status 1 status 0 system control state machine 3.3 vdc power supply +3.3 vdc typical application setup figure 2
preliminary data sheet #: tm040 p age 6 of 10 rev: p01 date: 10/24/02 ? copyright 2002 the connor-winfield corp. all rights reserved specifications subject to change without notice cntlb cntla mode status1status0 alarm rfl lor condition 0 0 free run 00100 0 0 free run 00110 0 1 reference #1 01000 normal operation 0 1 reference #1 01100 unit is in f ast acquire mode 0 1 reference #1 01010 output freq. is 15 ppm or more from free run mode freq. 0 1 reference #1 01001 selected reference signal is not detected and unit is in pseudo-hold over* 1 0 reference #2 10000 nor mal operation 1 0 reference #2 10100 unit is in fast acquire mode 1 0 reference #2 10010 output freq. is 15 ppm or more from free run mode freq. 1 0 reference #2 10001 selected reference signal is not detected and unit is in pseudo-hold over* 1 1 hold over 11100 1 1 hold over 11110 functional truth table table 8 *psuedo-hold over is a condition when the module is no longer tracking a reference and is holding the last output that was sent to the sync_out pin. variations in the output frequency are due only to the drift of the ocxo. ordering information stm-s3+ -l- (input reference frequency)(clock_out frequency)-(sync_out) nothing = 5v 8= 8 khz n= no output 02.048m = 2.048mhz l = 3.3v s= other 2= 2.048 mhz 016.384m = 16.384 mhz 5= 51.84 mhz 032.768m = 32.768 mhz 8= 8 khz 038.88 m = 38.88 mhz 9= 19.44 mhz 008.00k = 8 khz s= other example: mstm-s3+ -l-88-008.00k
preliminary data sheet #: tm040 p age 7 of 10 rev: p01 date: 10/24/02 ? copyright 2002 the connor-winfield corp. all rights reserved specifications subject to change without notice cntla cntlb reset ref #1 ref #2 free run hold over fast acquire mode alarm ocxo tcxo dds dsp 1/n status 1 status 2 rfl lor sync_out 8 khz output clk_out hold over good voltage regulation functional block diagram figure 3
preliminary data sheet #: tm040 p age 8 of 10 rev: p01 date: 10/24/02 ? copyright 2002 the connor-winfield corp. all rights reserved specifications subject to change without notice ? t rfl limit high frequency rfl limit low frequency sync_out rfl alarm 0 < t < 2.125 msec *the dds is updated only when the output changes level. the maximum update rate is 8 khz ? (nominal frequency) external reference input alarm ton a toff a 2 msec < t on < 6.125 msec 0 msec < t off < 2.125 msec a a loss of reference timing figure 4 rfl alarm timing figure 5 2 msec < t < 4.125 msec ? m change in control inputs operational mode indicator ? t m .030" pin land all solder and/or wire tags shall not extend more than .020" below pc board bottom surface .020" .020" max. mounting clearance dimensions figure 7 mode switch timing figure 6
preliminary data sheet #: tm040 p age 9 of 10 rev: p01 date: 10/24/02 ? copyright 2002 the connor-winfield corp. all rights reserved specifications subject to change without notice package dimensions figure 8
2111 comprehensive drive aurora, illinois 60505 phone: 630- 851- 4722 fax: 630- 851- 5040 www.conwin.com revision # revision datenotes p00 7/26/02 prelimi nary informational release p01 10/24/02 added order ing information
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